1. Field of the Invention
The present invention relates to a non-volatile memory, and more specifically to a non-volatile memory suitable for use in an integrated circuit such as a programmable logic circuit and a programmable signal processing circuit, the integrated circuit being electrically programmed and determined in its configuration after being packaged.
2. Prior Art
EPROMs (Erasable Programmable Read-Only Memory) and EEPROMs (Electrically Erasable and Programmable Read-Only Memory) are known as non-volatile memory devices which are now most widely used.
These devices output partly enormous contents stored therein by exetrnal addressing. As illustrated in FIG. 6, a two-dimensional array 10 of a floating gate avalanche injection MOS FET (hereinafter, referred to as a FAMOS) includes and addressing decoder 12 and a selector 14 additionally to memory cells 10A, . . . , 10N. The storage contents in the array is read out by previously providing electric charges to bit lines, selecting desired memory cells among the memory cells 10A, . . . , 10N, and imparting dynamical binary states to those bit lines, and further amplifying those states by an inverting amplifier 16 for example. While in storage of specifications of a logic circuit, e.g., a state of selection in the selector 14, all memory cells must hold a digital signal statically. Accordingly, in this case, memory cells, that do not allow dynamical read-out as just mentioned, are not useable. An additional circuit is neccessary, which converts the status of an EPROM cell or an EEPROM cell to a static voltage signal by any method.
Such a method of fully statically holding a digital signal using a FAMOS is disclosed in H. Gaw et. al., "A 100 ns 256K CMOS EPROM" ISSCC Dig. Tech. Papers, Feb. 1985, PP. 164-165, and in Saw-Ching Wong et al., "Novel circuit techniques for zero-power 25 ns CMOS erasable programmable logic device (EPLDs)" IEEE J. Solid-State Circuits. Vol. sc-21, No. 5 Oct. 1986.
The disclosed device basically includes as illustrated in FIG. 7, a latch 20, signal hold nodes Q, QN of the latch 20 and FAMOSs 22, 24 for switching to ground, the FAMOSs determining a signal voltage held in the latch 20 by being injected with electrons into floating gates thereof. More specifically, if electrons are injected into the floating gate only of the FAMOS 22, then the signal hold node Q holds a high level signal, while if electrons being injected into that only of the FAMOS 24, then the signal hold node Q holds a low level signal. In contrast, in a programmable signal processing device, a latch and a FAMOS array are independently arranged, the FAMOS array, which is similar to a typical EPROM device, is dynamically read out upon the initial stage of its operation, and data so read out is held by another latch.
Herein, when a FAMOS, which has been incorporated into a circuit instead of being array-shaped, is to be programmed, it is effectual to devise the circuit such that no high tension voltage is applied to peripheral circuit components of the FAMOS. One of such methods is disclosed in Japanese Patent Publication No. 57-16747, wherein floating gates of a plurality of FAMOSs are connected to a gate of an FET, and hot electrons produced in a channel region of the FET are injected into the floating gates of the FAMOSs.
Additionally, also for the typical array construction, Japanese Patent Publication No. 59-29155 discloses another technique where two FAMOSs for only programming and reading out, respectively, with their floating gates connected to each other are used to optimize respective device structures with respect to their operations, and assure high speed operation.
However, the aforementioned method, in which the non-volatile memory and the latch were separately disposed, are not of a general purpose type because the FAMOS array is dynamically read out at the initial stage of operation and hence additional time is required to some degree for operating the integrated circuit.
Furthermore, in the aforementioned fully static non-volatile memory, there are required many elements for one memory cell and high tension voltage is exerted on the signal hold nodes Q, QN shown in FIG. 7 for programming of the memory, so that all the involved elements must have a structure to withstand high voltage.
Owing to the reasons described above, every methods suffer from a very large area occupied by the memory cell which in turn hinders high integration of the device.